1. Field of the Invention
The present invention relates to an image inquiry circuit, and more particularly to an image inquiry circuit for retrieving an image similar to a small image from another image.
2. Description of the Related Art
An image inquiry circuit for comparing a reference image and a retrieval object image at a high speed is conventionally known. In such an image inquiry circuit, pixel processing circuits for the number of pixels of a small reference image are provided in a matrix manner. That is, the pixel processing circuits are connected to one after another in series in a column direction and finally to an image summing circuit. Also, the image processing circuits are connected to one after another in series in a row direction and a delay circuit is provided between the two adjacent rows of image processing circuits to delay an image signal by a processing time for one row.
This image inquiry circuit will be described below with reference to FIG. 1. FIG. 1 shows an example of the structure of the image inquiry circuit for comparing a retrieval object image with a reference image of a pixel array of m rows and n columns. In this image inquiry circuit, n pixel processing circuits PE.sub.i1, PE.sub.i2, PE.sub.i3 . . . PE.sub.in (i=1, 2, 3 . . . m) and a delay circuit (DL.sub.i) 2 are connected in series to form a row of pixel inquiry circuits. Then, the m row of pixel inquiry circuits are connected in series to form the image inquiry circuit having the pixel processing circuits of m rows and n columns. In this case, the image inquiry circuit having pixel processing circuits of m rows and n columns does not mean that the pixel processing circuits PE.sub.ij are arranged in m rows and n columns in space. However, it means that the image inquiry circuit can process a reference image of reference pixels arranged in a matrix manner of m rows and n columns.
Each of the pixel processing circuits 1 compares a reference pixel of the reference image with a corresponding retrieval pixel of the retrieval object image to calculate the difference between them. Then, each pixel processing circuit 1 outputs a square of the difference or an absolute value of the difference to the summing circuit (SU) 3. The summing circuit 3 performs a summing operation of the comparing results outputted from all the pixel processing circuits.
The delay circuit 2 functions as a shift register to shift received pixels in units of pixels, e.g., in units of bytes, if one pixel is represented by one byte. When the retrieval object image is read, a delay value of the delay circuit 2, namely, the number of stages of the register is set to (u-p), where u is the number of columns in the retrieval object image, and p is the number of columns in the reference image. When the retrieval object image is read into the image inquiry circuit, all the columns of retrieval pixels of the retrieval object image are shifted in a row direction to be always present in the same column of the image inquiry circuit.
In the image inquiry circuit of FIG. 1, (m.times.n) pixel processing circuits are provided. However, when the number of reference pixels of the reference image is smaller than (m.times.n), a specific value is written as "pixel non-presence data" in the pixel processing circuits in an excessive area where the reference pixels are not present. In this way, by using the above-mentioned pixel non-presence data, the outputs from the pixel processing circuits in the excessive area are excluded from the summing calculation performed by the summing circuit 3.
Referring to FIG. 1 again, the input of the first pixel processing circuit PE.sub.11 is connected to an input terminal i of the image inquiry circuit. Also, an output of the first pixel processing circuit PE.sub.11 is connected to an input of the second pixel processing circuit PE.sub.12. Moreover, the processed result of each pixel processing circuit is connected to the summing circuit 3. Then, the totally processed result is outputted from the summing circuit 3 via a terminal S.
An operation of the image inquiry circuit in FIG. 1 will be described below with reference to FIGS. 6A and 6B. FIG. 6A shows a reference image having an image size of q rows and p columns. Now, it is assumed that q=m and p=n. FIG. 6B shows a retrieval object image having an image size of v rows and u columns. A portion of the retrieval object image similar to the reference image is detected by the image inquiry circuit.
In order to set the reference image in the respective pixel processing circuits shown in FIG. 1, the delay values of the respective delay circuit 2 are set to 0. Then, the reference image is supplied from the terminal i in order of a.sub.1,1, a.sub.12, . . . , a.sub.lp, a.sub.21, a.sub.22, . . . , and further clock signals are supplied. Accordingly, the supplied reference image is passed through the respective pixel processing circuits connected to one after another in series. Finally, the reference image is held by the reference pixel holding circuits of the respective pixel processing circuits at a time when the pixel a.sub.qp is supplied.
Next, the delay value for (u-p) pixels is set in the delay circuits 2, and the retrieval object image is supplied from the input terminal i in order of b.sub.11, b.sub.12, . . . , b.sub.1u, b.sub.21, b.sub.22, . . . ,. At a time when the pixel b.sub.qp is inputted from the terminal i, the retrieval pixels b.sub.11 to b.sub.qp are held by (q.times.p) pixel processing circuits 12.
At that time, the differences between the reference pixel of the reference image and the retrieval pixel of the retrieval object image is calculated by each of the pixel processing circuits and then the summation of the squares of the differences is calculated by the summing unit 3. The summing result is outputted from the terminal S. Hereinafter, each time one retrieval pixel is supplied from the terminals i, the supplied retrieval pixels of the retrieval object image are compared with the reference pixels of the reference image. It should be noted that a comparison position is considered with respect to the pixel a.sub.11. Thus, the comparison position when the pixel a.sub.11 with the pixel b.sub.yx are compared is represented by (y-1, x-1).
There are the following problems in the conventional image inquiry apparatus. That is, there is a case where a plurality of image inquiry circuits, each of which shown in FIG. 1, are operated in parallel so as to increase the processing speed. In this case, the image inquiry is performed to regions of the retrieval object image by the respective image inquiry circuits. In the boundary between the regions of the retrieval object image, the pixels of the regions of the retrieval object image must be supplied in duplication to compare the retrieval object image with the reference image. As a result, this requires a data transferring ability which exceeds the parallel degree of the image inquiry circuits.
The reason why the regions of the retrieval object image must be supplied in duplication will be described below. For example, it is assumed that q=8 and v=256 in FIGS. 6A and 6B. In this case, there are comparison positions in a range between 0 and 248 in a vertical direction. If the comparison positions is divided into 2 groups to allow the retrieval object image to be inquired by use of two image inquiry circuits, two groups between 0 and 123 and between 124 and 248 are provided, for example. However, in the comparison position 123, the comparison between a.sub.1,1 and b.sub.124,1 is performed. Hence, it is necessary to supply 8 retrieval pixels of a portion of the retrieval object image from the pixel b.sub.124,1 to the pixel b.sub.131,u in order to obtain that comparison result. That is, in the boundary row, it is necessary that the retrieval pixels for (q-1) rows are supplied in duplication. Thus, the duplicate amount is increased in conjunction with the increase of the number of the boundaries.
Also, there is another problem in the conventional image inquiry circuit. It is difficult to increase a transferring rate of the retrieval pixels since the parallel degree is increased so that a load on a data transfer bus becomes larger. The reason thereof will be described below. In general, the data transfer bus is constructed so as to collectively transfer the retrieval pixels adjacent to each other in horizontal and vertical directions. For example, 8 pixels each having 8 bits are collectively transferred on the bus having a 64-bit width. Hence, latch circuits for a bus bit width are normally provided in front of the input terminals i of FIG. 1. For example, the retrieval pixels are transferred to the terminal i one by one after the eight pixels are stored in the latch circuits from the bus.
There is a case that eight image inquiry circuits, each of which is shown in FIG. 1, are provided in parallel to each other, and the latches having the width of the eight pixels are connected to the input terminal i of each image inquiry circuit. If the data for the eight pixels is circulated through each of the image inquiry circuits for each clock, the respective image inquiry circuits can receive the data for every eight clocks. In this case, the supply rate of the data is equal to the processing rate of the data. However, if a clock frequency is tried to be increased higher for high speed processing, a bus driving circuit is required to have a large driving ability such that the eight loads or latches can be driven. Actually, it is necessary that the bus width is made to be double, and the frequency of the clock signal is decreased.